module top(

input clk_125M,
input clk_125MV2,
input clk_12M5,
input led_sw,
output led_A,
output clkout,
input dummy

    );
wire reset_n = led_sw;



wire CLK_OUT1;
wire CLK_OUT2;
//wire CLKFB_OUT;
clk clkIns(
  .CLK_IN1(clk_125M),
  //.CLKFB_IN(CLKFB_OUT),
  // Clock out ports
  .CLK_OUT1(CLK_OUT1),
  //.CLK_OUT2(CLK_OUT2),
  //.CLKFB_OUT,
  // Status and control signals
  .RESET(~reset_n),
  .LOCKED()
);



assign clkout = CLK_OUT1;


reg led0;
assign led_A = led0;
reg [31:0] cnt0;
always @(posedge CLK_OUT1 or negedge reset_n) begin
  if (!reset_n) begin
  cnt0 <= 0;
  led0 <= 0;
  end else begin
  cnt0 <= cnt0 + 1'b1;
  if(cnt0==32'd26600000)begin
    cnt0 <= 0;
    led0 <= ~led0;
  end
  end
end

 

endmodule

